digital multi - p hase buck controller chl8225g/8g j une 21 , 201 3 | final | v1. 1 2 1 features ? 5 - phase & 8 - phase dual output pwm controller with phases flexibly assigned between loops 1 & 2 ? dynamic voltage control by 2 - bit parallel interface with gamer mode override and vmax setting ? input voltage management for up to 3 input voltages ? icritical monitor and phase current capture mode ? phase switching frequency from 200khz to 1.2mhz ? ir efficiency shaping features including variable gate drive, dynamic phase control ? programma ble 1 - phase or 2 - phase for light loads and active diode emulation for very light loads ? ir adaptive transient algorithm (ata) minimizes output bulk capacitors and system cost ? per - loop fault protection: ovp, uvp, ocp, otp ? i2c/smbus/pmbus system interface for telemetry of temperature, voltage, current & power for both loops ? non - volatile memory (nvm) for custom configuration ? compatible with ir atl and 3.3v tri - state drivers ? +3.3v supply voltage; 0oc to 85oc ambient operation ? pb - free, rohs, 6x6 40 - pin & 8x8 56 - pin qfn , msl2 package applications ? multiphase gpu systems pin diagram figure 1: chl8225g package top view description the chl8225g/8g are dual - loop , digital multi - phase buck controllers. the chl8225g drives up to 5 phases and the chl8228g drives up to 8 phases. they feature input voltage management allowing up to 3 input voltages to be monitored to ensure adequate power is delivered to the load. dynam ic voltage control is provided by 4 registers which are programmed through i2c/smbus/pmbus and then selected using a 2 - bit parallel bus for fast access. the chl8225g/8g includes the ir efficiency shaping technology to deliver exceptional efficiency at mini mum cost across the entire load range. ir variable gate drive optimizes the mosfet gate drive voltage as a function of real - time load current. ir dynamic phase control adds and drops phases based upon load current. the chl8225g/8g can be configured to ente r 1 - phase operation and active diode emulation based upon load current or by command. ir s unique adaptive transient algorithm (ata), based on proprietary non - linear digital pwm algorithms, m inimizes output bulk capacitors . the i2c/pmbus interface can commun icate with up to 16 chl8225g/8g - based vr loops. device configuration and fault parameters are defined using the ir digital power design center ( dpdc ) gui and stored in on - chip nvm. the chl8225g/8g provides extensive ovp, uvp, ocp and otp fault protec tion and includes thermistor based temperature sensing with vrhot signal. the chl8225g/8g includes numerous features like register diagnostics for fast design cycles and platform differentiation, simplifying vrd design and enabling fastest time - to - market w ith its set - and - forget methodology. figure 2 : chl822 8g package top view s m b _ d i o p w m 5 v r h o t _ i c r i t # v r t n r c s m i s e n 5 i s e n 4 i s e n 3 v s e n s m b _ c l k p w m 4 v r _ r e a d y _ l 1 i r t n 3 i r t n 4 i r t n 5 r c s p t s e n v i d s e l 0 p w m 3 e n a b l e v 1 8 a r r e s v c c i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 r c s m _ l 2 r c s p _ l 2 v a r _ g a t e v i d s e l 1 v i d s e l _ l 2 v i n s e n _ a u x 1 v r _ r e a d y _ l 2 v c c v i n s e n v r t n _ l 2 v s e n _ l 2 1 2 7 8 5 6 3 4 1 0 9 3 0 2 9 2 4 2 3 2 6 2 5 2 8 2 7 2 1 2 2 4 1 g n d c h l 8 2 2 5 g 4 0 p i n 6 x 6 q f n t o p v i e w 1 2 1 6 1 4 1 9 1 3 1 7 1 5 2 0 1 8 1 1 3 9 3 5 3 7 3 2 3 8 3 4 3 6 3 1 3 3 4 0 s m b _ d i o p w m 5 i s e n 6 e n a b l e v r t n r c s m i s e n 5 i s e n 4 i s e n 3 p w m 6 v s e n s m b _ c l k p w m 4 v r _ r e a d y _ l 1 i r t n 3 i r t n 4 i r t n 6 i r t n 5 r c s p t s e n v r h o t _ i c r i t # p w m 3 v i n s e n v i d s e l 1 _ l 2 v 1 8 a r r e s v c c i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 v i n s e n _ a u x 1 r c s m _ l 2 r c s p _ l 2 v b o o t v r h o t 2 v m a x v i d s e l 0 v i d s e l 1 v i d s e l 0 _ l 2 v r _ r e a d y _ l 2 v c c v i n s e n _ a u x 2 p w m 7 v r t n _ l 2 v s e n _ l 2 5 7 g n d c h l 8 2 2 8 g 5 6 p i n 8 x 8 q f n t o p v i e w 5 5 5 1 5 3 4 8 5 4 5 0 5 2 4 7 4 9 5 6 4 6 4 5 4 3 4 4 1 2 7 8 5 6 3 4 1 0 9 1 2 1 1 1 4 1 3 1 6 2 0 1 8 2 3 1 7 2 1 1 9 2 4 2 2 1 5 2 5 2 6 2 8 2 7 4 2 4 1 3 6 3 5 3 8 3 7 4 0 3 9 3 3 3 4 3 1 3 2 2 9 3 0 i s e n 8 e n _ l 2 t s e n 2 v a r _ g a t e p w m 8 i s e n 7 i r t n 7 i r t n 8
digital multi - p hase buck controller chl8225g/8g j une 21 , 201 3 | final | v1. 1 2 2 ordering information chl822 ? g D ? ? ? ? ? figure 3: chl8225g top view enlarged package packing qty part number qfn t= 3000 ty=4900 chl8225g - 00crt chl8225g - 00crty qfn t= 3000 chl8225g - xxcrt 1 qfn t=3000 ty= 2600 chl8228g - 00crt chl8228g - 00crt y qfn t= 3000 chl8228g - xxcrt 1 notes: 1 . xx indicates c ustomer s pecific c onfiguration f ile . figure 4 : chl822 8g top view enlarged t C tape & reel / ty - tray r C package type (qfn) c C operating temperature (commercial standard) xx C configuration file part n umber 5: chl8225g 8: chl8228g s m b _ d i o p w m 5 v r h o t _ i c r i t # v r t n r c s m i s e n 5 i s e n 4 i s e n 3 v s e n s m b _ c l k p w m 4 v r _ r e a d y _ l 1 i r t n 3 i r t n 4 i r t n 5 r c s p t s e n v i d s e l 0 p w m 3 e n a b l e v 1 8 a r r e s v c c i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 r c s m _ l 2 r c s p _ l 2 v a r _ g a t e v i d s e l 1 v i d s e l _ l 2 v i n s e n _ a u x 1 v r _ r e a d y _ l 2 v c c v i n s e n v r t n _ l 2 v s e n _ l 2 1 2 7 8 5 6 3 4 1 0 9 3 0 2 9 2 4 2 3 2 6 2 5 2 8 2 7 2 1 2 2 4 1 g n d c h l 8 2 2 5 g 4 0 p i n 6 x 6 q f n t o p v i e w 1 2 1 6 1 4 1 9 1 3 1 7 1 5 2 0 1 8 1 1 3 9 3 5 3 7 3 2 3 8 3 4 3 6 3 1 3 3 4 0 s m b _ d i o p w m 5 i s e n 6 e n a b l e v r t n r c s m i s e n 5 i s e n 4 i s e n 3 p w m 6 v s e n s m b _ c l k p w m 4 v r _ r e a d y _ l 1 i r t n 3 i r t n 4 i r t n 6 i r t n 5 r c s p t s e n v r h o t _ i c r i t # p w m 3 v i n s e n v i d s e l 1 _ l 2 v 1 8 a r r e s v c c i s e n 2 i s e n 1 i r t n 1 i r t n 2 p w m 2 p w m 1 v i n s e n _ a u x 1 r c s m _ l 2 r c s p _ l 2 v b o o t v r h o t 2 v m a x v i d s e l 0 v i d s e l 1 v i d s e l 0 _ l 2 v r _ r e a d y _ l 2 v c c v i n s e n _ a u x 2 p w m 7 v r t n _ l 2 v s e n _ l 2 5 7 g n d c h l 8 2 2 8 g 5 6 p i n 8 x 8 q f n t o p v i e w 5 5 5 1 5 3 4 8 5 4 5 0 5 2 4 7 4 9 5 6 4 6 4 5 4 3 4 4 1 2 7 8 5 6 3 4 1 0 9 1 2 1 1 1 4 1 3 1 6 2 0 1 8 2 3 1 7 2 1 1 9 2 4 2 2 1 5 2 5 2 6 2 8 2 7 4 2 4 1 3 6 3 5 3 8 3 7 4 0 3 9 3 3 3 4 3 1 3 2 2 9 3 0 i s e n 8 e n _ l 2 t s e n 2 v a r _ g a t e p w m 8 i s e n 7 i r t n 7 i r t n 8
digital multi - p hase buck controller chl8225g/8g j une 21 , 201 3 | final | v1. 1 2 3 functional block dia gram figure 5 : chl8225g & chl8228g functional block diagram t s e n v i n s e n v o l t a g e a d c v s e n v r t n c o n t r o l a n d m o n i t o r i n g v o u t 1 _ e r r o r v o u t 2 _ e r r o r p w m 1 p w m 2 p w m 3 p w m 4 p w m 5 r e f e r e n c e , o s c i l l a t o r , s t a t e c o n t r o l , i n t e r f a c e s , r e g i s t e r s a n d n v m v i d s e l 1 a d c c l o c k s m u x c l o c k s p h a s e _ p e r i o d _ 1 p h a s e _ p e r i o d _ 2 v 3 _ 3 i o u t v i n t e m p f a u l t b u s s y s t e m c l o c k i o u t v i n t e m p v o u t f a u l t b u s s y s t e m c l o c k v i d _ 1 v i d _ 2 c u r r e n t a d c m o d e c o n t r o l v a r _ g a t e l d o v c c 1 . 8 v v 1 8 a v i d s e l 0 v i d s e l 0 _ l 2 v r h o t _ i c r i t # v r _ r e a d y _ l 1 v r _ r e a d y _ l 2 p h a s e _ p e r i o d _ 1 p h a s e _ p e r i o d _ 2 r r e s r c s p r s c m a f e _ 1 v i d _ 1 s m b _ d i o s m b _ c l k v i n s e n _ a u x 1 v i n s e n _ a u x 2 ( c h l 8 2 2 8 g o n l y ) v m a x v b o o t o n l y f o r c h l 8 2 2 8 g o n l y f o r c h l 8 2 2 8 g v r h o t 2 e n p w m 6 p w m 7 p w m 8 o n l y f o r c h l 8 2 2 8 g p w m g e n e r a t o r i s e n 1 i r t n 1 i s e n x i r t n x i s e n y i r t n y i s e n z i r t n z i t o t _ 1 i t o t _ 2 i p 1 i p x i p y i p z . . . . . . . . . . . . . . . . . . c h l 8 2 2 5 g c h l 8 2 2 8 g x 3 4 y 4 5 z 5 8 e n _ l 2 v i d s e l 1 _ l 2 v s e n _ l 2 v r t n _ l 2 r c s p _ l 2 r s c m _ l 2 a f e _ 2 v i d _ 2 i t o t _ 2 i p 5 i p 6 i p 8 . . . . . . o n l y f o r c h l 8 2 2 8 g t s e n 2 ( c h l 8 2 2 8 g o n l y ) m o n i t o r a d c i p 1
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